1. Field of the Invention
Embodiments presented herein relate generally to computing systems, and, more particularly, to a method for two-dimensional (2D) training for double data rate (DDR) memory data eye training using reference voltages (Vrefs) and signal timing.
2. Description of Related Art
Electrical circuits and devices that execute instructions and process data have evolved becoming faster, larger and more complex. With the increased speed, size, and complexity of electrical circuits and data processors, data eye training has become more problematic, particularly in DDR memory systems. As technologies for electrical circuits and processing devices have progressed, there has developed a greater need for efficiency, reliability and stability, particularly in the area of DDR memory data eye training. However, considerations for algorithm processing, overall system boot-up performance, as well as system complexity introduce substantial barriers to efficiently training data eyes in DDR memory systems. The areas of acceptable data eye formation, Vref tolerances (e.g., voltage margins) and data transfer speeds are particularly problematic, for example, in systems that utilize and/or support different types of interchangeable microprocessors or DDR RAM.
Typically, modern implementations for data eye training in DDR systems, as noted above, have taken the approach of solving data eye training in the time domain, limited to a nominal Vref value setting. However, this approach has undesirable drawbacks. For example, time domain training does not allow for Vref tolerances to be adequately met or utilized, nor does time domain training allow for adequate system boot reliability across a variety of hardware platforms.
Embodiments presented herein eliminate or alleviate the problems inherent in the state of the art described above.